1. Field of the Invention
The present invention relates to high density memory devices, and particularly to memory devices which can include thin film memory cells arranged to provide a three-dimensional 3D array.
2. Description of Related Art
High density memory devices are being designed that comprise arrays of flash memory cells, or other types of memory cells. In some examples, the memory cells comprise thin film transistors which can be arranged in 3D architectures.
3D memory devices have been developed in a variety of configurations that include a plurality of thin film, active strips separated by insulating material. One type of 3D memory device that uses thin film transistors as the memory cells is known as a 3D vertical gate structure such as is described in our co-pending U.S. patent application Ser. No. 13/078,311; filed 1 Apr. 2011, entitled MEMORY ARCHITECTURE OF 3D ARRAY WITH ALTERNATING MEMORY STRING ORIENTATION AND STRING SELECT STRUCTURES (US 2012/0182806 A1, published 19 Jul. 2012) which is incorporated by reference as if fully set forth herein. The 3D vertical gate structure includes a plurality of stacks of thin film strips with word line structures that overlie the stacks, such that the portions of the word line structures that extend vertically between the stacks act as the word lines for the memory cells at the cross-points with the strips. The thin film active strips in this structure, and in other memory structures, may be lightly doped and have no body contact, which can isolate them from sources of charge carriers needed during operation of the device. Conditions in which sources of charge carriers are insufficient can harm operating efficiencies.
It is desirable to provide a structure for three-dimensional integrated circuit memory with higher array efficiency.